1. Field of the Invention
The present invention relates to a synchronous dynamic random access memory (SDRAM) and, more particularly, to a memory controller controlling the SDRAM, a semiconductor integrated circuit monolithically integrating the memory controller on a single semiconductor chip, and a method for controlling a memory.
2. Description of the Related Art
An SDRAM is widely used as a frame memory in a moving picture experts group (MPEG) codec and as a memory in a main storage or the like of a computer. The SDRAM has a plurality of banks used as storage areas. A memory controller controlling the SDRAM supplies a command to the SDRAM in response to a command request from an external device. The commands include an active command, a write command, a read command, and a precharge command and the like. The memory controller generates one command in one clock cycle in accordance with the command request associated with the banks. The memory controller includes state machines associated with the banks in order to generate the commands at appropriate times, and the state machines manage command generation. The term “state machine” refers to the circuit transferring a plurality of states in a preset order, based on an input condition. The technique has been proposed of efficiently generating the command by supervising the states of each state machines associated with the banks.
Mutually supervising the states of the state machines requires, for the input conditions, state information signal of the other state machines and state information signal of the other state machines after a lapse of one clock cycle. Since the circuit scale and complexity of the state machines increase in proportion to the number of the input conditions, the time required for designing the memory controller and the circuit scale of the memory controller increase. Since the state machines exchange information with each other, a timing loop causing unstable data occurs.